Low Complexity Design Space Exploration from Early Specifications

Performance evaluation and design space exploration from early specifications is still a time consuming, experience and technology dependant issue in the design process. However, evaluation of architectural alternatives at an early stage of the design process is important because the choices made have a critical impact on the system final characteristics (area, performances, power consumption, flexibility, . . . ). To address those problems, we propose an original exploration methodology based on area / delay estimations and a case study targeting modern FPGAs. Two main steps compose the estimation flow: a structural estimation step that performs automatic exploration of several RTL architectural solutions and a physical estimation step that performs a technology mapping of the RTL solutions to the target FPGA. Experiments conducted on Xilinx (VirtexE) and Altera (Apex20K) FPGAs for a 2D Discrete Wavelet Transform and a G722 speech coder lead to an average error of 10% for temporal values and 18% for area estimations, starting from algorithmic descriptions given in the C language. The low complexity of the method allows fast exploration of many design parameters such as parallelism, target device, resources allocation, scheduling, clock period. Thanks to this methodology, the complexity of the design space exploration process is significantly reduced and permits to reach quickly a reliable solution meeting with both the design constraints (time to market, target FPGA) and the device architecture (cost, performance). Index Terms Design Space Exploration, area / delay estimation, C specification, H/CDFG representation, graph scheduling, architectural synthesis, technology projection, FPGA devices.